this is information on a product in full production . june 2014 docid025241 rev 1 1/8 ESDAVLC6-1V2 single line low capacitance transil? for esd protec tion datasheet - production data features ultra small pcb area = 0.09 mm2 unidirectional device very low diode capacitance low leakage current rohs compliant applications where transient over voltage protection in esd sensitive equipment is required, such as: smart phones and accessories portable multimedia devices and accessories tablets description the ESDAVLC6-1V2 is a single line unidirectional transil diode designed specially for the protection of integrated circuits into portable equipment and miniaturized electronics devices subject to esd transient overvoltage. the device is ideal for applications where both reduced printed circuit board space and high esd protection level are required. complies with following standards: iec 61000-4-2 level 4: C 8 kv contact discharge C 15 kv air discharge figure 1. functional diagram tm: transil is a trademark of stmicroelectronics st01005 ESDAVLC6-1V2 pin1 pin 2 www.st.com
characteristics ESDAVLC6-1V2 2/8 docid025241 rev 1 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 8 15 kv t j operating temperature range -40 to +125 c t stg storage temperature range - 55 to +150 c t l maximum lead temperature for soldering during 10 s 2 60 c symbol p arameter v = breakdown voltage v = stand-off voltage v = clamping voltage i = peak pulse current brrm cl pp i = leakage current @ v rm rm = line capacitance c line r = dynamic resistance d v i v cl v br v rm i f v f i rm i pp slope: 1/r d table 2. electrical characteristics (values, t amb = 25 c) symbol parameter test conditions value unit min. typ. max. v br breakdown voltage i r = 1 ma 6 v i rm leakage current v rm = 3 v 50 na c line line capacitance, i/o to gnd v r = 0 v, f = 1 mhz, v osc = 30 mv 5 7 pf
docid025241 rev 1 3/8 ESDAVLC6-1V2 characteristics 8 figure 5. l s21 attenuation measurement figure 3. esd response to iec 61000-4-2 (typical values, +8 kv contact discharge) figure 4. esd response to iec 61000-4-2 (typical values, -8 kv contact discharge) 20 v/div 20 ns/div v : esd peak voltage pp v :clamping voltage @ 30 ns cl v :clamping voltage @ 60 ns cl v :clamping voltage @ 100 ns cl 1 2 3 4 55 v 2 18 v 4 32 v 3 1 88 v 20 v/div -73 v -33 v -18 v -6 v 20 ns/div v : esd peak voltage pp v :clamping voltage @ 30 ns cl v :clamping voltage @ 60 ns cl v :clamping voltage @ 100 ns cl 1 1 2 2 3 4 4 3 s21 (db) 10m 30m 100m 300m 1g 3g 10g -21 -18 -15 -12 - 9 -6 - 3 0 esdavlc6 -1v2 f (hz)
package information ESDAVLC6-1V2 4/8 docid025241 rev 1 2 package information epoxy meets ul94, v0 lead-free package in order to meet environmental requirements, st off ers these devices in different grades of ecopack ? packages, depending on their level of environmenta l compliance. ecopack ? specifications, grade definitions and product statu s are available at: www.st.com . ecopack ? is an st trademark. figure 6. package dimensions figure 7. footprint recommendation 50 m 50 m 50 m 50 m 75 m 75 m 200 m 200 m 20 205 m 20 25 m 10 450 m 20 solder pad pcb opening a = 225 m b = 225 m c = 50 md = 180 m e = 180 m f = 100 m g = 530 mh = 40 m i = 112.5 m j = 270 m a b c d e f g h i j
docid025241 rev 1 5/8 ESDAVLC6-1V2 recommendation on pcb assembly 8 3 recommendation on pcb assembly 3.1 stencil opening design stencil opening thickness: 80 m figure 8. recommended stencil window position 3.2 solder paste 1. use halide-free flux, qualification rol0 accordin g to ansi/j-std-004. 2. no clean solder paste recommended. 3. offers a high tack force to resist component dis placement during pcb movement. 4. solder paste with fine particles: type 4 (powder particle size 20-38 m per ipc j-std- 005). k = 180 m l = 180 m m = 150 m solder pad pcbopening stencil aperture (thickness stencil: 80 m) k l m n n = 30 m
recommendation on pcb assembly ESDAVLC6-1V2 6/8 docid025241 rev 1 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition ca pabilities of the placement system, not the outline centering. 3. tolerance of 0.02 mm is recommended. 4. 1.0 n placement force is recommended. too much p lacement force can lead to squeezed out solder paste and cause solder joints t o short. too low placement force can lead to insufficient contact between package an d solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bot tom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (a ll the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed vi a is recommended instead of open vias. 2. the position of tracks and open vias in the sold er area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 3.5 reflow profile figure 9. st ecopack ? recommended soldering reflow profile for pcb mount ing note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6 c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
docid025241 rev 1 7/8 ESDAVLC6-1V2 ordering information 8 4 ordering information figure 10. ordering information scheme 5 revision history table 3. ordering information order code marking weight base qty delivery mode ESDAVLC6-1V2 l 0.041 mg 20 000 tape and reel esda - vlc 6 1 v2 esd array very low capacitance breakdown voltage 6 = 6 v min. directional = idirectional 1 un package v = st01005 package 2 = 2 pads table 4. document revision history date revision changes 05-jun-2014 1 first issue
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